Virtual phase buried channel CCD

ABSTRACT

A virtual phase, buried channel CCD with the usual metal gate/oxide structure replaced by a reverse biased junction (possibly a heterojunction) or Schottky barrier is disclosed. Such gate substitution for a standard three phase or multiphase CCD and other devices compatibly fabricated with such gate are also disclosed.

This application is a continuation of application Ser. No. 618,621 filedJune 8, 1984 now abandoned.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor charge transfer devices, and,more particularly, to virtual phase, buried channel charge coupleddevices.

Charge transfer devices including charge coupled devices (CCDs) are wellknown monolithic semiconductor devices and are used in variousapplications such as shift registers, imagers, infrared detectors,memories, etc. For example, Wolfe and Zissis, Eds, The Infrared Handbook(1978), devote chapter 12 to CCDs and with emphasis on their use ininfrared signal processing. The traditional three phase CCD is an arrayof adjacent cells (each cell, in essence, being a MIS capacitor) andoperates by tying the gates of every third cell together so that varying(clocking) the gate voltages in three phases transfers charge packetsfrom cell to adjacent cell. This traditional CCD would be basicallyformed by covering a p-type substrate with oxide and patterning metalgates on the oxide. In such a device electrons are transferred in thesubstrate essentially along the interface with the oxide, which leads topoor transfer efficiency due to traps at the interface. Further, suchdevices have problems including breakdown of the gate oxide, complicatedgate connections, blooming (a charge packet larger than the capacity ofa cell will overflow into adjacent cells), etc.

The problem of interface trap induced low transfer efficiency can besolved by using a buried channel CCD structure (BCCD) in which thecharge packets are confined to and flow in a channel that lies in thesubstrate beneath the interface. Thus the charge packets are held awayfrom the interface traps and do not exhibit low charge transferefficiency. However, this arrangement increases dark current generationat the interface. A BCCD can be fabricated by forming an n-type layer onthe p-type substrate and then covering it with an oxide layer andpatterned metal gates on the oxide. The n-type layer is thin and isfully depleted by the gate clocking action and bias applied to ann+-type junction attached to the end of the channel. The conduction andvalence energy band diagram for the device shows the bands that are bentand have a minimum in the n-type layer. This conduction band minimum isthe location where the charge packets accumulates and are transferredfrom cell to cell by variations in the gate bias voltages changing therelative energy band minima between cells. For example, see, Sze,Physics of Semiconductor Devices (2d Ed 1980) pp 423-427.

A BCCD with the standard metal gate/oxide replaced by a p-type gateregion to form a p-n junction with the n-type channel layer is alsoknown; see, for example, E. Wolsheimer and M. Kleefstra, ExperimentalResults on Junction Charge-Coupled Devices, 29 IEEE Trans. Elec. Dev.1930 (1982). In such a junction BCCD, the control of the energy bands inthe buried channel is accomplished by varying the reverse bias on thep-n junction. But such a junction BCCD may have large leakage currentsbetween the adjacent p-type gate regions and also has difficulty inachieving smooth transitions of the buried channel potential energylevels between cells.

The problems associated with the complicated gate structure of suchthree phase BCCDs are overcome with the virtual phase CCD as describedin Hynecek, U.S. Pat. No. 3,2729,752. A virtual phase CCD needs only asingle set of gates and a single clocking bias and operates on theprinciple of selectively doping different regions of each cell so thatclocking the gate affects only the energy bands in a portion of eachcell and, indeed, drives them from below to above the fixed energy bandsin the remainder of each cell. The doped region that shields thisremainder of a cell from the effect of the clock bias of the gatevoltage is normally called the "virtual gate".

However, all of the prior art devices still suffer from problems ofoxide breakdown, blooming, leakage currents, and nonsmooth cell-to-cellpotential energy profile transitions.

SUMMARY OF THE INVENTION

A preferred embodiment of the present invention provides a BCCD devicewith cells built incorporating a p-type substrate covered by an n-typelayer (which will include the buried channel) which in turn is coveredby a p-type layer (channel barrier) in which an n-type gate region isformed. Additional implants in the p-type channel barrier complete thecell by forming the virtual barrier and well; then n-type gate definesthe clocked well and clocked barrier regions (these regions aredistinguished from each other by the additional implant in the p-typelayer) and the virtual well and virtual barrier regions (again theseregions are distinguished from each other by the additional implant inthe p-type layer) make up the remainder of the cell. This firstpreferred embodiment BCCD cell operates in the same manner as a standardvirtual phase, buried channel CCD with MOS gates; the MOS gate hasessentially been replaced by a reverse biased n - p junction.

A second preferred embodiment BCCD cell has an n-type buried channellayer on a p-type substrate with a p-type virtual gate region on theburied channel separated from a p-type channel barrier region with ann-type clocked gate subregion on the buried channel. Implants in theburied channel and the channel barrier distinguish the virtual barrierand well and the clocked barrier and well, respectively. A thirdpreferred embodiment uses a Schottky barrier in place of the reversebiased n-p junction clocked gate of the second preferred embodiment. Anda fourth preferred embodiment employs the same structure as the firsttwo preferred embodiments but uses a different material for the n-typegate so that a heterojunction is formed which permits adjustment ofinfrared response when the cell is used as a photosite. Furtherpreferred embodiments include a standard, multiphase BCCD with thereverse biased n-p junction gates separated by oxide with underlyingp-type regions forming virtual wells, a memory cell with the reversebiased n-p junction as a transfer region, and a charge detectorincluding junction field effect and vertical bipolar transistors.

All of these preferred embodiments overcome the problems of breakdown ofthe gate oxide by eliminating the necessity for the oxide. Further, allof these embodiments have a built in anti-blooming capability becauseoverflow charge will automatically be drained by the reverse biasedjunction or the Schottky barrier junction. These preferred embodimentsalso solve the problems of leakage between gates and nonsmoothtransitions of conduction energy band levels between calls. And theability to fabricate both the CCD cells and the charge detector (outputnode for the CCD), including transistors, from essentially the sameprocess steps allows for simplicity and process control.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross section of a standard MOS virtual phaseburied channel CCD;

FIGS. 2A-D show the conduction and valence bands for the device of FIG.1;

FIG. 3 is a schematic cross section of a first preferred embodiment CCDwith reversed bias junction gates;

FIG. 4 shows the doping profiles for the device of FIG. 3;

FIGS. 5A-B show the conduction and valence bands for the device of FIG.3;

FIGS. 6A-E show the fabrication steps for making the device of FIG. 3;

FIG. 7 shows a second preferred embodiment CCD with Schottky junctiongates;

FIG. 8 shows the conduction and valence bands for the device of FIG. 7;

FIG. 9 shows the device of FIG. 3 adapted to a multi phase CCD;

FIG. 10 shows a preferred embodiment random access memory cell;

FIG. 11 is a schematic cross section of a preferred embodiment BCCDoutput node;

FIG. 12 is a schematic cross section of a preferred embodiment junctionfield effect transistor; and

FIG. 13 is a schematic cross section of a preferred embodiment verticalbipolar transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In order to understand the preferred embodiments and their operation, wefirst consider the standard virtual phase, buried channel CCD and itsoperation. Turning first to the upper portion of FIG. 1, we see that thestandard virtual phase BCCD, generally designated 11, includes a p-typesilicon substrate 13, a n-type layer 15 on substrate 13, p-type regions17 formed in the upper portion of layer 15, oxide layer 19, gate 21which may be metallization, and donor implants 23, 24 and 25 in then-type layer 15. The operation of device 11 will be described below andis illustrated by the buried channel potential energy profile shown inthe lower portion of FIG. 1 directly below the corresponding regions ofdevice 11. These regions are given the following names: p-type regions17 are called virtual gates (or virtual electrodes), the portion oflayer 15 below both virtual gate 17 and donor implant 25 is called thevirtual well, the portion of layer 15 below virtual gate 17 but notbelow donor implant 25 is called the virtual barrier, the portion oflayer 15 not below virtual gate 17 but below donor implant 23 is calledthe clocked well and the portion of layer 15 below neither virtual gate17 nor donor implant 23 is called the clocked barrier.

FIGS. 2A-D illustrate the conduction and valence energy bands and showthe buried channel feature. In particular, from left to right, FIG. 2Ashows the bands as a function of distance measured from the metal gatevertically downwards through the clocked barrier region and with thegate 21 at about approximately the same bias as substrate 13. This bandbending arises from the depletion of n-type layer 15, which isrelatively thin. The curvature of the bands shown in FIG. 2A shows theexistence of the buried channel. If a free electron were introduced intolayer 15, then it would fall to the minimum of the conduction band,which is located away from the oxide 19 silicon interface.

FIG. 2B shows the change in the bands of FIG. 2A upon application of anegative bias to gate 21. In essence, the potential energy at the buriedchannel (the minimum of the conduction band) is raised (for electrons).FIG. 2C shows the corresponding band diagram for the virtual barrierregion. FIG. 2D compares the conduction band for the clocked well regionwith the conduction band for the clocked barrier region, the valancebands being omitted for simplicity. The lower band is for the clockedwell region and has a lower minimum due to the positive donor charge 23,which is also illustrated in FIG. 2D. Analogously, the energy bands forthe virtual well region are similar to those of FIG. 2C, except that thedonor change 25 depresses the minimum as in FIG. 2D. The bands shown inFIG. 2C do not move up and down with a change in the bias of gate 21because virtual gates 17 are connected to the p-type channel stops (notshown in FIG. 1 but which run parallel to the buried channel and whichare connected to the p-type substrate 13) and thus are effectivelypinned at the bias of substrate 13.

The operation of device 11 can now be explained. Turning to the lowerportion of FIG. 1, the energy levels for an electron in the buriedchannel (conduction band minimum) are shown for the various regions ofdevice 11 and for gate 21 being both approximately at substrate 13 biasand at a negative bias with respect to substrate 13. Starting with anelectron in the virtual barrier region, the operation is as follows.First the electron falls into the virtual well region, this is showndiagramatically by arrow 27 in the energy level diagram part of FIG. 1.Next, if gate 21 is turned on (negative with respect to substrate 13),then the electron will remain in the virtual well because the energylevels of both adjacent regions are higher, the energy level of theclocked barrier in this state is denoted 29 in FIG. 1. When the gate 21is turned off (bias approximately equal to substrate bias 13) then theenergy level of the clocked barrier drops to the position 31 and theelectron passes from the virtual well into the clocked barrier asillustrated by arrow 33 in FIG. 1. The electron continues and falls intothe clocked well 35 as shown by arrow 37. The electron remains in theclocked well until gate 21 is turned on at which time the energy levelsof the clocked barrier and clock wells both rise as shown by arrow 39 inFIG. 1. Once the energy level of the clocked well increases to greaterthan that of virtual barrier level 41, the electron falls out of theclocked well and into the virtual barrier as shown by arrow 43. Thus theelectron is back in the virtual barrier region but in the cell adjacentthe starting cell of device 11. Movement of the electron to furthercells is just a repeat of the same steps and clocking of the gate 21.With the operation of the virtual phase device 11 now in mind, we candescribe the structure in operation of the preferred embodiments of thepresent invention.

The upper portion of FIG. 3 shows a schematic cross section of somecells of first preferred embodiment BCCD device 51. Device 51 includes alightly doped (1E15 acceptors/cm³) p-type substrate 53, n-type layer 55with a doping level of approximately 5E16 and a thickness ofapproximately 370 nm, p-type layer 57 with doping of approximately 8E16and a thickness of approximately 250 nm, p-type layer 59 of dopingapproximately 1E18 and a thickness of approximately 120 nm, oxideregions 61, virtual gates 63 which are p-type and extend to the channelstops as previously described in device 11 and will be further describedbelow, donor implants 65 in layer 55 and covering approximately half ofthe bottom side of virtual gates 63, and acceptor implants 67 in regions57 and covering approximately one half (but not necessarily) of theunderside of the regions 59. Note that the extent of implants 65 and 67(illustrated as approximately one half of regions 63 and 59,respectively) could be varied to advantage in certain deviceapplications. FIG. 4 shows the doping profile and is a graph of thelogarithm of the doping concentration plotted horizontally versus thedistance from the top of device 51 at region 59 and plotted verticallydownwards. These regions have the following self-explanatory names:region 59 is the gate, region 57 the channel barrier, region 55 theburied channel, and region 53 the substrate.

If a positive bias with respect to substrate 53 is applied to gate 59,then the energy bands appear as in FIG. 5A-D. In particular, FIG. 5Ashows the bands for gate 59 being about 6 volts with respect tosubstrate 53; note that the depletion extends far into substrate 53 dueto its light doping. Of course, buried channel 55 and channel barrier 57are fully depicted (it is not necessary that the channel barrier isdepleted of holes for all gate bias conditions), whereas gate 59 isheavily doped and only partially depleted. The form of energy bands inFIG. 5A is similar to that of FIG. 2A. If the bias on gate 59 is variedrelative to substrate 53, then the bands of FIG. 5A move up and downanalogously with the movement of the bands illustrated in FIGS. 2A and2B when the gate 21 bias of device 11 is varied.

FIG. 5B shows the energy bands under the virtual gate 63; these areanalogous with the bands of FIG. 2C, and as with virtual gate 17,virtual gate 63 is connected to the channel stops and thus bands areinvariant as the bias on clocked gate 59 is varied. Donor implants 65and acceptor implants 67 both affect the energy bands in a manneranalogous to the donor implants 23 and 25 in device 11; namely, thebands are shifted a fixed amount near the minimum. Consequently, device51 has the same definition of the buried channel as the minimum of theenergy bands and the same partitioning of a cell into a clocked barrierregion, a clocked well region, a virtual barrier region, and a virtualwell region as device 11. Thus, device 51 will operate in the samemanner as device 11. This operation is illustrated in the lower portionof FIG. 3 which shows the energy levels at the conduction band minimumand flow of electrons in the manner of the lower portion of FIG. 1.

Although the operation of device 51 is analogous to the operation ofdevice 11, the advantage of device 51 include the elimination of theoxide 19 of device 11. No oxide breakdown under gate bias can occur indevice 51 because the only oxide 61 is for isolation of the busses forthe clocked gates 59 and can be made relatively thick. Also, the reversebias of the junction formed by clocked gate 59 and channel barrierregion 57 acts as a drain for overflow charge associated with blooming;thus, as an electron charge packet in a cell is increased in size thepresence of charge raises and flattens the minimum in the energy bands(both in device 11 and in device 51), and a portion of the charge packetwill overflow into adjacent cells in device 11. In contrast, overflowcharge from a large charge packet will spill over into channel barrierregion 57 and then into clock gate 59 rather into an adjacent cell indevice 51; this is not possible in device 11 because the oxide 19 isnonconducting. Also, note that channel barrier regions 57 preventselectrons from clocked gate 59 from falling into the buried channel andsaturating it; recall that region 55 is depleted. Additionally, leakagecurrent between clocked gates 59 and the virtual gates 63 is negligibleprovided the reverse bias junction breakdown is avoided, yet the buriedchannel conduction bands have smooth transitions from cell to cell.

Further understanding of the operation of device 51 can be obtained froma description of a preferred embodiment method of fabrication of device51. Such preferred embodiment method of fabrication is as follows. Thestarting material can be a substrate (100) p+-type silicon with a 10micron thick epitaxial layer of p-type with carrier concentration1E15/cm³. Standard self aligned thick oxide (SATO) step sequences areapplied to define the active region and peripheral region of the device.The following discussion will focus only on the active regions of thedevice.

A 200A oxide is grown in the active areas after the original SATOnitride and oxide have been removed. This step is followed by a uniformphosphorous buried channel implant (no mask) with the dose preferablybeing 1.8E12/cm² and energy 300keV. Next a mask patterning and a highenergy low dose boron implant defines the channel stop region. FIG. 6Ashows a schematic cross section indicating the p+-type substrate 52,p-type epitaxial layer 53, thick oxide 71, 200A oxide layer 73,phosphorous doped buried channel region 55, photoresist pattern 75, andboron implanted channel stop regions 77. Note that the view in FIG. 6Ais perpendicular to the view in FIG. 3 and that the transfer of chargepackets will be perpendicular to the paper in FIG. 6A.

After the boron and phosphorous implants and necessary photoresistclean-up, a patterned layer of nitride and oxide is deposited as shownin FIG. 6B; note FIG. 6B is a view parallel to the view of FIG. 3 andperpendicular to the view of FIG. 6A. Nitride layer 79 is preferably1800 A thick and oxide layer 81 is preferably 4000 A thick. After theoxide 81 and nitride 79 are patterned, a boron implant is used to definevirtual gates 63, which extend across the channel stops 77. Next a wellmask photoresist 83 is patterned and a phosphorous well implant 65 ismade. After removal of photoresist and clean-up, oxide 81 is removed andthe device 51 is subject to oxidation. Optionally, before the oxidationand oxide 81 removal an additional nitride 79 etch is applied to form anundercut in nitride 79 which is used to control the interface regionsbetween the virtual and clocked gates; such an optional undercut isdesignated by 85 in FIG. 6B. This undercut step allows for precisecontrol of the electrical field between the clocked gate 59 and virtualgate 63. This control is necessary for achieving a smooth energy leveltransition from cell to cell and at the same time provides a highreverse breakdown voltage between gates 59 and 63. This is in contrastto the prior art BCCD with p-type gates where generation of potentialbarriers between the gates to prevent leakage between the gatesnecessarily led to creation of nonsmooth cell to cell energy leveltransition profiles and formed parasitic wells and barriers whichincreased the transfer inefficiency. Typically, undercut 85 is one totwo microns, and nitride 79 and oxide 81 are five to ten microns wide.

After oxidation, the remaining nitride 79 is removed and the device isready for formation of the clocked gate and barrier; see FIG. 6C, andthe oxide 87 may be 4000 A thick. If the optional undercut 85 of nitride79 had been performed, then oxide 87 will extend beyond virtual gate 63by the amount of the undercut, this is shown as the distance 89 in FIG.6C. Other combinations of materials are possible in place of the nitrideand oxide stack; for example, polysilicon and nitride. Next the p-typechannel barrier region 57 is formed by boron implant, preferably at adensity of 2.4E12/cm² at 90 keV. Next the n-type clocked gate 59 isformed by phosphorous implant at a density of 5E12/cm² at 40keV. Lastly,the clocked barrier implant of boron a density of 1.6E12/cm² at 70keV ismade after barrier mask 91 is patterned. The resulting structure isshown in FIG. 6D. FIG. 6E shows a simplified plan view of the foregoingstructure, and because channel stops 77 are only of a low dose they canbe depleted by the clocked gate 59, so an additional high does, lowenergy channel stop implant is made at the connection of virtual gate 63with channel stop 77. This implant is designated 93 and is of sufficientenergy to connect the virtual gate 63 with substrate 52. This high doseimplant step is most conveniently made after the virtual gate andbarrier implants.

To achieve high frequency operation, the high sheet resistance of theclocked gate 59 must be overcome; this is done by covering the devicewith an oxide layer and forming contact holes in the oxide to theclocked gates 59, preferably at regions 95 (FIG. 6E) over the channelstops 77. A low resistance layer, such as polysilicon, molybdenum,titanium-tungsten, etc. is deposited on the oxide layer and makescontact to clocked gates 59 through the openings 95. Preferably such lowresistance layer is in the form of a buss located over the channel stops77. Such buss location is advantageous if the cells are being used foroptical or infrared detection.

The gate structure of device 51 has low leakage current because thegate-channel barrier is always reversed biased.

Device 51 can be incorporated into many different products, such as areaimagers, frame transfer, interline transfer, line addressed, as well aslinear imagers. The relative dimensions of the virtual gate 63 and theclocked gate 59 can change depending on the application. For example,use only of the virtual gates 63 are photosites for the collection ofphotogenerated charge and interfacing this with another CCD structure orcharge sensing amplifier is possible.

A second preferred embodiment includes the use of Schottky barriers inplace of the gate and channel barriers of the first preferred embodimentdevice 51. More particularly, FIG. 7 shows a schematic cross sectionalview of second preferred embodiment device, generally denoted 101.Device 101 includes a p-type substrate 103, and n-type channel region105, p-type virtual gate regions 107, donor implants 109, metal gates111 which form Schottky barriers with layer 105, donor implants 113, andchannel stops which are not shown and run parallel to the cross sectionof FIG. 7. Metal gates 111 extend from channel stop to channel stop andthus span both the p-type channel stops and the n-type channel region105 (this is analogous to the gates 59 of device 51 extending beyondchannel barrier region 57 onto channel stop 77, as shown in FIG. 6E).Thus if metal 111 is chosen so hat its work function lies between thework function of the p-type material of layer 103 and the n-typematerial of layer 105, then Schottky barriers will be formed both at thejunction between gate 111 and layer 105 and gate 111 and the channelstops. Note that if the metal 111 work function is too close to thep-type material work function, then there will be a substantial holecurrent from metal gate 111 to the channel stops which will cause largepower dissipation and ohmic potential drops along buss lines as well asin the substrate. Conversely, if the work function of the metal 111 istoo close to the work function of the n-type material, there will be alarge dark current (barrier leakage current) that will saturate theburied channel and make device 101 inoperable.

The operation of device 101 is analogous to that of devices 11 and 51explained above. In particular, the Schottky barrier formed by metalgate 111 and n-type layer 105 is reversed biased; this, along with thedepletion due to the n-p junction between layers 105 and 103, causes theconduction band energy level and the valence energy band to have aminimum as shown in FIG. 8. As with devices 11 and 51, the minimum ofthe energy bands for device 101 defines the buried channel. Note thatFIG. 8 also shows the conduction band and the valence band for theSchottky barrier formed between metal gate 111 and the p-type channelstop; these energy bands are shown as dotted lines in FIG. 8.

The effect of implants 109 and 113 in device 101 is analogous to theeffect of implants 23 and 25 in device 11 and implants 65 and 67 indevice 51 in that the implants, in effect, split the regions below thevirtual gates 107 into the virtual barrier and virtual well regions inthe buried channel and split the regions under metal gates 111 into theclocked barrier and clocked well regions in the buried channels.Analogous to the lower portions of FIGS. 1 and 3, the lower portion ofFIG. 7 shows the energy level minimum of the conduction band in theburied channel for the virtual barrier and well and clocked barrier andwell regions. Again, the effect of clocking metal gate 111 is to shiftthe conduction band energy levels in the clocked barrier and wellregions above and below the fixed conduction band levels in the virtualbarrier and well regions, as illustrated by the vertical arrows in thelower portion of FIG. 7.

Device 101 can be fabricated using steps similar to those describedabove for fabrication of device 51; although fabrication of device 101may be simpler.

A particular application for device 101 is as an infrared sensor. Thebarrier for electron flow from metal 111 into n-type region 105 can beadjusted so that infrared excited electrons can surmount the barrier andbe collected in the buried channel region and thereby detected. Theproblem of a large dark current is overcome in such a device by coolingthe device to low temperatures as is typical for infrared detectors.

A third preferred embodiment uses reversed bias heterojunctions for thegates. More particularly, if gates 59 of device 51 were of asemiconductor material with a smaller energy band gap than the energyband gap of the material of channel barrier 57, then the electronbarrier for electrons flowing from the gate into the buried channel canbe adjusted by material selection. This would be useful in infrareddetecting devices.

The upper portion of FIG. 9 is a schematic cross section of fourthpreferred embodiment device 121 which is, in essence, device 51converted to a multiphase BCCD. Device 121 includes p-type siliconsubstrate 123, n-type layer 125 which contains the buried channel,p-type regions 127 which are the channel barriers, n+-type regions 129which are the clocked gates, acceptor implants 131 in regions 127 whichdefine the clocked barrier from the clocked well, p+-type regions 133which are the virtual gates and connect to the channel stops (parallelto but not shown in the cross section of FIG. 9), and oxide 135. Each ofclocked gates 129 - channel barriers 127 junctions is reversed biasedand each of gates 129 may be independently biased relative to the twoadjacent gates. Such independent biasing may transfer charge as shown bythe buried channel energy levels in the lower portion of FIG. 9.

Device 121 has low leakage current between gates 129 and between gates129 and virtual gates 133 due to the reverse bias of the gate 129 -channel barrier 127 junction.

The upper portion of FIG. 10 shows a schematic cross section of thefifth preferred embodiment of the invented device, which is a singlecell of a random access memory and generally denoted 151. Device 151includes p-type silicon substrate 153, n-type layer 155 which s a buriedchanel, p+-type region 157 which is a channel stop, n+-type region 159which connects to a work line 160, p-type region 161 which is a channelbarrier, n+-type region 163 which connects to a bit line 164, p+-typeregion 165 which induces a storage region in channel 155, and oxide 167.The view in FIG. 10 is perpendicular to the analogous view in FIGS. 1,3, 7, and 9 because the transfer of charge packets in device 151 is notalong channel 155 but rather a transfer back and forth between thestorage region in the channel under region 165 and the region in thechannel under region 159. Analogous to device 51, the reverse bias onthe n-p junction of regions 163 and 161 (i.e., the bit line bias)controls such transfer, as illustrated by arrow 171 in the channelenergy level diagram in the lower portion of FIG. 10. Arrow 173illustrates the level change for read/write a charge packet from/intothe storage region. Again, the reverse bias on such n-p junction leadsto low leakage currents.

Further preferred embodiments of the inventive device are shown in FIGS.11, 12, and 13, and illustrate the output node and amplifiers whichcould be used with a BCCD made of cells of device 51. In particular, theupper portion of FIG. 11 shows a schematic cross sectional view of anoutput node for a BCCD, and a lower portion of FIG. 11 shows the energylevels at the conduction band minimum and the flow of electrons in thesame manner as the lower portions of FIGS. 1 and 3. The output node isgenerally denoted 181 and includes p-type substrate 183, n-type buriedchannel layer 185, p-type channel barrier 187, n-type diode region 189,n-type reset gate region 191, n-type floating diffusion region 193,virtual gate regions 195, virtual barrier region 197, virtual wellimplants 199, output diode line 201, reset gate line 203, and floatingdiffusion line 205. The left edge of the upper portion of FIG. 11,including channel barrier 57 and clocked gate region 59, represents thelast cell in the BCCD, and upon clocking of this last cell, illustratedby arrow 207 in the energy level diagram in the lower portion of FIG.11, the charge packet in this last cell spills over the virtual barrierbelow region 197 and into the well below the floating diffusion region193, as illustrated by arrow 209. This charge packet increases theenergy level inthe well below floating diffusion region 193, asillustrated by arrow 211; this increase in energy is sensed by floatingdiffusion line 205 and proceed, as more fully described below. After thecharge packet is sensed, the well below floating diffusion region 193 isreset by reset gate line 203 being turned on, which lowers the energylevel below reset gate region 191 and channel barrier 187, as shown byarrow 213; this lowering connects the well below floating diffusionregion 193 to the virtual well below implants 199 and the region belowoutput diode region 189 in the right hand portion of FIG. 11. The chargepacket is thus drained off by output diode line 201 and the energy levelin the well below floating diffusion 193 reestablished at the outputdiode level 215. Next, the reset gate line 203 is turned off and theenergy level below reset gate region 191 and channel barrier 187 israised, as illustrated by arrow 213, to again isolate the well belowfloating diffusion region 193 from the output diode region 189, and thefloating diffusion line 205 is ready to sense the next charge packetdelivered from the cell at the left hand portion of FIG. 11. Note thatthe structure illustrated in the upper portion of FIG. 11 is of the samegeneral format as that of device 51, and can be simply fabricated by afew mask changes. In particular, the channel barriers below floatingdiffusion region 193 and output diode region 189 are omitted, the lefthand virtual gate 195 only has implants that create a virtual barrierrather than a virtual well, and the virtual gates 195 in the center andright hand portion of FIG. 11 have implant 199 to create a virtual wellbeneath them. Thus, the total output node illustrated in FIG. 11 caneasily be fabricated upon and along with a BCCD incorporating device 51cells.

FIG. 12 is a schematic cross sectional view of a junction field effecttransistor which can be used to amplify the charge packet signal sensedby floating diffusion line 205. Thi field effect transistor, generallydenoted 221, also is fabricated in the general format of device 51 andinlcudes p-type substrate 223, n-type channel layer 225, n+-type drainregion 227, p-type gate region 229, n+-type source region 231, drainpolysilicon 233, drain metallization 235, source polysilicon 237, sourcemetallization 239, gate metallization 241, gate implants 243, plusimplants in the gate, source, and drain regions 229, 231, and 227.Device 221 is shown with enclosed topology; that is, device 221 issymmetric about axis 245 which is necessary to isolate the p+gate fromthe p+channel stops or peripheral field oxide. Floating diffusion line205 may be connected to gate 241 and device 221 used to amplify thecharge packet signal sensed in device 181. Again, device 221 iscompatible with the processing of device 51, although the thick oxide247 must be opened to form the gate 241 metallization contact with gateregion 229.

In addition to the junction field effect transistor 221, a verticalbipolar transistor may be fabricated with process steps compatible tothose for fabricating device 51. A schematic cross section of such abipolar transistor, generally denoted 261, is shown in FIG. 13 andincludes p-type substrate 263, n-type collector layer 265, n+-typecollector region 267, n+ polysilicon 269, collector metallization 271,collector implant 273, p-type base 275, base metallization 277, thickoxide 279, n+ polysilicon 281, and emitter metallization 283. As withdevice 221, thick oxide 279 must be opened up in device 261 to make thebase contact and the emitter 281. Note that the n+ polysilicon used indevice 261 and 221 is the same as the n+ polysilicon used for buses indevice 51; that is, there is no extra polysilicon step needed tofabricate devices 221 and 261. Also, the collector region 267 and device261 and the source region 231 and drain region 227 and device 221 aresimply the same as the clocked gate region 59 in device 51 but withchannel barrier omitted. Further implant 273 is just the virtual wellimplant 65 in device 51. Again, no extra fabrication steps are needed.Lastly, device 261 has enclosed topology by making the collectorsymetrical about the axis 285 to isolate the base p1 region from the p+peripheral regions.

In all of the preferred embodiment descriptions above, various itemshave been omitted for simplicity, such as protective oxides,metallizations, connections, and so forth.

The preferred embodiments may be modified in various ways, such asvarying the doping levels, type of doping, materials, and dimensions.

I claim:
 1. A gate structure for a buried channel charge coupled device,comprising:(a) a substrate of a first conductivity type; (b) a buriedchannel of opposite conductivity type on said substrate; (c) asemiconductor channel barrier on said buried channel, said channelbarrier and said buried channel of opposite conductivity types; and (d)a semiconductor gate region on said channel barrier, said gate regionand said channel barrier of opposite conductivity types; (e) a gateelectrode of said first conductivity type in said buried channel; and(f) an isolation oxide over said gate electrode isolating channelbarrier portions and gate electrode portions over said channel barrierportions from adjacent channel barrier portions and gate electrodeportions.
 2. The gate structure of claim 1, wherein:(a) the thicknessand doping level of said channel barrier are characterized by means toprovide substantially full depletion of said channel barrier duringportions of the operation of said device in which said buried channel isdepleted except for signal charge and said gate region is clocked.
 3. Agate structure as set forth in claim 2, further including a donorimplant in said buried layer beneath said gate electrode and closelyadjacent thereto.
 4. A gate structure as set forth in claim 3; furtherincluding an acceptor implant in said buried layer beneath a portion ofsaid gate portion.
 5. A gate structure as set forth in claim 1, furtherincluding a donor implant in said buried layer beneath said gateelectrode and closely adjacent thereto.
 6. A gate structure as set forthin claim 5, further including an acceptor implant in said buried layerbeneath a portion of said gate region.